DESIGN OF MICROPROCESSORS AND ACCELERATORS

Course objectives

KNOWLEDGE AND UNDERSTANDING. RTL design, VHDL/SystemVerilog, microprocessor architectures. CAPABILITY TO APPLY KNOWLEDGE AND UNDERSTANDING. Digital circuit design, FPGA/ASIC synthesis, microprocessor design/programming. MAKING AUTONOMOUS JUDGEMENTS. Evaluation of design alternatives and technologies to be used. COMMUNICATE SKILLS. Specification and modeling of digital systems, team work LEARNING SKILLS. Any subsequent advancement on digital circuits, architectures and programming.

Channel 1
MAURO OLIVIERI Lecturers' profile

Program - Frequency - Exams

Course program
RECALL: THE DESIGN FLOW Abstraction levels, Analysis and verification tools REGISTER TRANSFER LEVEL DESIGN OF HARDWARE ACCELERATORS Register transfer level (RTL) synthesis, Design example: a simple edge detection filter for image processing, Data-path synthesis analysis, In-depth concepts of RTL timing REGISTER TRANSFER LEVEL DESIGN OF PROCESSOR CORES Specification of a very simple microprocessor for edge detection, RTL design of the microprocessor, in-depth concepts on the control-path implementation, Quantitative laws on digital system performance. FUNDAMENTAL MECHANISMS OF MICROPROCESSOR ARCHITECTURES General ideas, Rules of the RISC approach, fundamentals of post-RISC architectures, the RISC-V instruction set architecture, quick overview of superscalar architectures, VLIW architectures, instruction scheduling DESIGN OF SPECIAL PURPOSE CO-PROCESSORS case study: vector processors for high performance computing and embedded computing
Prerequisites
knowledge of hardware description languages, digital circuits
Books
Waine Wolf, Modern VLSI Design, Prentice Hall. Hennessy, J., Patterson, D., Computer Architecture: a quantitative approach, Elsevier. Hennessy, J., Patterson, D., Computer Organization and Design - RISC-V Edition, Elsevier Slides and articles available at: http://vlsi.diet.uniroma1.it and on the Google Classroom
Teaching mode
lectures, flipped class exercises, occasionalmente lezioni in remoto
Exam mode
written and oral exam + compulsory student project
Bibliography
to be specified in the classroom
Lesson mode
lectures, flipped class exercises, occasionalmente lezioni in remoto
MAURO OLIVIERI Lecturers' profile

Program - Frequency - Exams

Course program
RECALL: THE DESIGN FLOW Abstraction levels, Analysis and verification tools REGISTER TRANSFER LEVEL DESIGN OF HARDWARE ACCELERATORS Register transfer level (RTL) synthesis, Design example: a simple edge detection filter for image processing, Data-path synthesis analysis, In-depth concepts of RTL timing REGISTER TRANSFER LEVEL DESIGN OF PROCESSOR CORES Specification of a very simple microprocessor for edge detection, RTL design of the microprocessor, in-depth concepts on the control-path implementation, Quantitative laws on digital system performance. FUNDAMENTAL MECHANISMS OF MICROPROCESSOR ARCHITECTURES General ideas, Rules of the RISC approach, fundamentals of post-RISC architectures, the RISC-V instruction set architecture, quick overview of superscalar architectures, VLIW architectures, instruction scheduling DESIGN OF SPECIAL PURPOSE CO-PROCESSORS case study: vector processors for high performance computing and embedded computing
Prerequisites
knowledge of hardware description languages, digital circuits
Books
Waine Wolf, Modern VLSI Design, Prentice Hall. Hennessy, J., Patterson, D., Computer Architecture: a quantitative approach, Elsevier. Hennessy, J., Patterson, D., Computer Organization and Design - RISC-V Edition, Elsevier Slides and articles available at: http://vlsi.diet.uniroma1.it and on the Google Classroom
Teaching mode
lectures, flipped class exercises, occasionalmente lezioni in remoto
Exam mode
written and oral exam + compulsory student project
Bibliography
to be specified in the classroom
Lesson mode
lectures, flipped class exercises, occasionalmente lezioni in remoto
  • Lesson code10621422
  • Academic year2025/2026
  • CourseElectronics Engineering
  • CurriculumElectronics Engineering (percorso valido anche ai fini del conseguimento del doppio titolo italo-statunitense o italo-francese) - in lingua inglese
  • Year1st year
  • Semester2nd semester
  • SSDING-INF/01
  • CFU6