SALVATORE PONTARELLI

Progettazione di Sistemi Digitali (Canale A-L) a.a. 2024/25

Orari: 

Giovedì dalle 08:00 alle 10:00,  in aula 4, via De Lollis

Venerdì dalle 10:00 alle 13:00,  in aula 4, via De Lollis 

Le lezioni si terranno in aula A1 Capozzi del Dipartimento SOMF in Via Caserta 

Gli studenti del corso sono pregati di iscriversi tramite google classroom al corso con codice blb53dw (https://classroom.google.com/c/MTczNjk2NDI1MjI5?cjc=blb53dw) utilizzando l'email fornita dall'ateneo.

Architetture degli elaboratori per l’intelligenza artificiale  a.a. 2024/25

Orari: 

Martedì dalle 16:00 alle 18:00 in aula C Edificio "Guido Castelnuovo"

Mercoledì dalle 14:00 alle 16:00 in aula C Edificio "Guido Castelnuovo"

Gli studenti del corso sono pregati di iscriversi tramite google classroom al corso con codice 3w7cmbk (https://classroom.google.com/c/NzAzNTcxNTcyNDA1?cjc=3w7cmbk) utilizzando l'email fornita dall'ateneo.

Per informazioni sui corsi è possibile contattare il docente all'indirizzo salvatore.pontarelli@uniroma1.it

Ricevimento studenti

Giovedi dalle 10:30 alle 11:30 in studio (viale Regina elena, 295, Edificio E, stanza 105), previa prenotazione via e-mail.

Salvatore Pontarelli started his research activity in the Defect and Fault Tolerance group of the University of Rome “Tor Vergata” working on the design of highly reliable systems for space applications. In this context, he collaborated with various public bodies and private companies (Italian Space Agency, European Space Agency, Thales-Alenia Space, Syderal) in the design of highly reliable digital systems for satellites. Some of these systems are used in several satellites currently in orbit (Gaia satellite and MTG (Meteosat Third Generation) constellation).

In 2009 he began his collaboration with CNIT by studying the use of FPGAs to accelerate algorithms for internet traffic inspection (Deep Packet Inspection) used in Intrusion Detection System. Subsequently, he worked on the design and optimization of structures based on Bloom filters and hash tables, with the aim of improving their efficiency in terms of memory resources and energy consumption. He received three Cisco Research Awards for his research in this field. He has collaborated with various manufacturers of internet network devices (Cisco and Mellanox Technologies). The results of his research activity are used on several Ethernet switching chips. He has participated in several research projects funded by public bodies and private companies, also acting as Principal Investigator and as Work Package manager.

He published more than 60 articles in archival journals and more than 70 contributions in proceedings of international conferences and he holds 11 patents. He has been Guest Editor for several scientific journals (Elvevier and IEEE), is Associate Editor for IEEE Transactions on nanotechnology and IET Electronics Letters and has held organizational roles (Program Chair, General Chair) in various IEEE conferences.