Computer Architecture
Course objectives
General objectives: The goal of the course on Computer Architecture is to make students understand the principles used to design modern computers. In particular, the course deals with the internal structure of the microprocessor and the ideas that have allowed the extraordinary evolution of computing power over the last 30 years. such as pipelining, caching, branch prediction, and multi-processing. Specific objectives: The course covers the basic principles of microprocessor organization and the concepts of pipelining, caching, branch prediction, virtualization and multi-processing. Furthermore, the course covers assembly programming. Knowledge and understanding: Students will acquire knowledge about the organization of the microprocessor MIPS, as implementation of the general ideas that are part of the objectives of the course. Furthermore, the student will acquire knowledge on how the assembly programs are structured, including data structures, standard programming paradigms and recursion. Application of knowledge and understanding: The knowledge is applied to the MIPS architecture, enabling students to understand the implications of programming choices on the performance of programs on specific hardware. This result is obtained through programming and performance evaluation exercises. Autonomy of judgment: The student will be able to understand the problems related to the performance of the software on specific hardware and to independently evaluate their characteristics. Communication skills: The course is not concerned with explicit objectives on communication skills, except to instruct on the rigorous presentation of formal topics. Ability of learning: The course lays the foundations for the comprehension of the modules constituting the course of Operating Systems and of all the courses of programming, including the programming of parallel systems.
Channel 1
Davide Polese
Lecturers' profile
Program - Frequency - Exams
Course program
Introduction to computer and MIPS instructions. Representation of RISC-V instructions in assembly language, use of memory to save variables and data. Use of logical operators. Control structures, vectors and matrices. (~15 hours)
System calls and functions. Stack management. Nested function calls and single/multiple recursion. (~15 hours)
Single-clock RISC-V CPU design. RISC-V assembly instruction design for single clock cycle architecture. Introduction to pipeline and hazards. CPU design with a pipeline. Management of data and control hazards in pipelined architectures. (~15 hours)
Introduction to caching. Cache associativity and multilevel caching. Virtual memory, multiple caches and exception handling. (~15 hours)
The reported number of hours is indicative and may vary according to the learning needs and context.
Prerequisites
Good preparation for the main high-school courses, especially Mathematics, is required. The student is assumed to be familiar with the contents of the course entitled “Progettazione di sistemi digitali” [Digital systems design], held in the first semester of the first year of this programme.
Books
[ITA] D. A Patterson J. L. Hennessy. “Struttura e progetto dei calcolatori”, Progettare con RISC-V, 2a edizione, Zanichelli, 2023. ISBN: 9788808199669.
[EN] D. A. Patterson and J. L. Hennessy. “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, 2nd edition, Morgan Kaufmann, 2020. ISBN: 9780128245583.
Frequency
Although not mandatory, attendance is recommended to acquire knowledge keeping pace with the ongoing lectures and be well trained for the exam test at the end of the course.
Exam mode
The exam is based on a mixed test. The practical part of the test consists of programming exercises to be done in the laboratory. Furthermore, homework will be assigned during the course to track the ongoing learning status. The written part is about the foundational concepts of computer architectures as per the program of the course.
The written test determines the final grade. To consider the exam as passed, the practical test on assembly programming must be successfully completed.
The exams will be held in compliance with the University regulations.
Bibliography
The course is fully covered by the book and no other references are needed.
Lesson mode
The course is based on in-class lectures and demonstrations, plus assembly programming homework assignments.
Davide Polese
Lecturers' profile
Program - Frequency - Exams
Course program
Introduction to computer and MIPS instructions. Representation of RISC-V instructions in assembly language, use of memory to save variables and data. Use of logical operators. Control structures, vectors and matrices. (~15 hours)
System calls and functions. Stack management. Nested function calls and single/multiple recursion. (~15 hours)
Single-clock RISC-V CPU design. RISC-V assembly instruction design for single clock cycle architecture. Introduction to pipeline and hazards. CPU design with a pipeline. Management of data and control hazards in pipelined architectures. (~15 hours)
Introduction to caching. Cache associativity and multilevel caching. Virtual memory, multiple caches and exception handling. (~15 hours)
The reported number of hours is indicative and may vary according to the learning needs and context.
Prerequisites
Good preparation for the main high-school courses, especially Mathematics, is required. The student is assumed to be familiar with the contents of the course entitled “Progettazione di sistemi digitali” [Digital systems design], held in the first semester of the first year of this programme.
Books
[ITA] D. A Patterson J. L. Hennessy. “Struttura e progetto dei calcolatori”, Progettare con RISC-V, 2a edizione, Zanichelli, 2023. ISBN: 9788808199669.
[EN] D. A. Patterson and J. L. Hennessy. “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, 2nd edition, Morgan Kaufmann, 2020. ISBN: 9780128245583.
Frequency
Although not mandatory, attendance is recommended to acquire knowledge keeping pace with the ongoing lectures and be well trained for the exam test at the end of the course.
Exam mode
The exam is based on a mixed test. The practical part of the test consists of programming exercises to be done in the laboratory. Furthermore, homework will be assigned during the course to track the ongoing learning status. The written part is about the foundational concepts of computer architectures as per the program of the course.
The written test determines the final grade. To consider the exam as passed, the practical test on assembly programming must be successfully completed.
The exams will be held in compliance with the University regulations.
Bibliography
The course is fully covered by the book and no other references are needed.
Lesson mode
The course is based on in-class lectures and demonstrations, plus assembly programming homework assignments.
Channel 2
ALESSANDRO CHECCO
Lecturers' profile
Program - Frequency - Exams
Course program
Introduction to computer and MIPS instructions. Representation of RISC-V instructions in assembly language, use of memory to save variables and data. Use of logical operators. Control structures, vectors and matrices. (~15 hours)
System calls and functions. Stack management. Nested function calls and single/multiple recursion. (~15 hours)
Single-clock RISC-V CPU design. RISC-V assembly instruction design for single clock cycle architecture. Introduction to pipeline and hazards. CPU design with a pipeline. Management of data and control hazards in pipelined architectures. (~15 hours)
Introduction to caching. Cache associativity and multilevel caching. Virtual memory, multiple caches and exception handling. (~15 hours)
The reported number of hours is indicative and may vary according to the learning needs and context.
Prerequisites
Good preparation for the main high-school courses, especially Mathematics, is required. The student is assumed to be familiar with the contents of the course entitled “Progettazione di sistemi digitali” [Digital systems design], held in the first semester of the first year of this programme.
Books
[ITA] D. A Patterson J. L. Hennessy. “Struttura e progetto dei calcolatori”, Progettare con RISC-V, 2a edizione, Zanichelli, 2023. ISBN: 9788808199669.
[EN] D. A. Patterson and J. L. Hennessy. “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, 2nd edition, Morgan Kaufmann, 2020. ISBN: 9780128245583.
Frequency
Although not mandatory, attendance is recommended to acquire knowledge keeping pace with the ongoing lectures and be well trained for the exam test at the end of the course.
Exam mode
The exam is based on a mixed test. The practical part of the test consists of programming exercises to be done in the laboratory. Furthermore, homework will be assigned during the course to track the ongoing learning status. The written part is about the foundational concepts of computer architectures as per the program of the course.
The written test determines the final grade. To consider the exam as passed, the practical test on assembly programming must be successfully completed.
The exams will be held in compliance with the University regulations.
Bibliography
The course is fully covered by the book and no other references are needed.
Lesson mode
The course is based on in-class lectures and demonstrations, plus assembly programming homework assignments.
ALESSANDRO CHECCO
Lecturers' profile
Program - Frequency - Exams
Course program
Introduction to computer and MIPS instructions. Representation of RISC-V instructions in assembly language, use of memory to save variables and data. Use of logical operators. Control structures, vectors and matrices. (~15 hours)
System calls and functions. Stack management. Nested function calls and single/multiple recursion. (~15 hours)
Single-clock RISC-V CPU design. RISC-V assembly instruction design for single clock cycle architecture. Introduction to pipeline and hazards. CPU design with a pipeline. Management of data and control hazards in pipelined architectures. (~15 hours)
Introduction to caching. Cache associativity and multilevel caching. Virtual memory, multiple caches and exception handling. (~15 hours)
The reported number of hours is indicative and may vary according to the learning needs and context.
Prerequisites
Good preparation for the main high-school courses, especially Mathematics, is required. The student is assumed to be familiar with the contents of the course entitled “Progettazione di sistemi digitali” [Digital systems design], held in the first semester of the first year of this programme.
Books
[ITA] D. A Patterson J. L. Hennessy. “Struttura e progetto dei calcolatori”, Progettare con RISC-V, 2a edizione, Zanichelli, 2023. ISBN: 9788808199669.
[EN] D. A. Patterson and J. L. Hennessy. “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, 2nd edition, Morgan Kaufmann, 2020. ISBN: 9780128245583.
Frequency
Although not mandatory, attendance is recommended to acquire knowledge keeping pace with the ongoing lectures and be well trained for the exam test at the end of the course.
Exam mode
The exam is based on a mixed test. The practical part of the test consists of programming exercises to be done in the laboratory. Furthermore, homework will be assigned during the course to track the ongoing learning status. The written part is about the foundational concepts of computer architectures as per the program of the course.
The written test determines the final grade. To consider the exam as passed, the practical test on assembly programming must be successfully completed.
The exams will be held in compliance with the University regulations.
Bibliography
The course is fully covered by the book and no other references are needed.
Lesson mode
The course is based on in-class lectures and demonstrations, plus assembly programming homework assignments.
- Lesson code1015881
- Academic year2024/2025
- CourseInformatics
- CurriculumMetodologico
- Year1st year
- Semester2nd semester
- SSDINF/01
- CFU6
- Subject areaFormazione informatica di base