DIGITAL INTEGRATED SYSTEM ARCHITECTURES
Course objectives
KNOWLEDGE AND UNDERSTANDING. Digital VLSI circuits, RTL design, VHDL, microprocessor architectures. CAPABILITY TO APPLY KNOWLEDGE AND UNDERSTANDING. Digital circuit design, FPGA/ASIC synthesis, microprocessor design/programming. MAKING AUTONOMOUS JUDGEMENTS. Evaluation of design alternatives and technologies to be used. COMMUNICATE SKILLS. Specification and modeling of digital systems. LEARNING SKILLS. Any subsequent advancement on digital circuits, architectures and programming.
Channel 1
MAURO OLIVIERI
Lecturers' profile
FRANCESCO MENICHELLI
Lecturers' profile
Program - Frequency - Exams
Course program
- Digital circuit simulation with NGSPICE
- VHDL simulation with Modelsim
- RTL synthesis on FPGA: synthesizable VHDL, synthesis with Xilinx
- RTL synthesis on ASIC: synthesis with Synopsys Design Compiler
Prerequisites
Digital electronic circuits, VHDL language programming.
Books
The laboratory is based on course handouts dristributed on elearning.uniroma1.it
Frequency
Mandatory attendance for the laboratory experieces
Exam mode
Written open questions on the applications developed during the laboratory.
- Lesson code10589407
- Academic year2025/2026
- CourseElectronics Engineering
- CurriculumElectronics Engineering (percorso valido anche ai fini del conseguimento del doppio titolo italo-statunitense o italo-francese) - in lingua inglese
- Year1st year
- Semester2nd semester
- SSDING-INF/01
- CFU9