Electronics Engineering

RECALL: THE DESIGN FLOW Abstraction levels, Analysis and verification tools REGISTER TRANSFER LEVEL DESIGN OF HARDWARE ACCELERATORS Register transfer level (RTL) synthesis, Design example: a simple edge detection filter for image processing, Data-path synthesis analysis, In-depth concepts of RTL timing REGISTER TRANSFER LEVEL DESIGN OF PROCESSOR CORES Specification of a very simple microprocessor for edge detection, RTL design of the microprocessor, in-depth concepts on the control-path implementation, Quantitative laws on digital system performance. FUNDAMENTAL MECHANISMS OF MICROPROCESSOR ARCHITECTURES General ideas, Rules of the RISC approach, fundamentals of post-RISC architectures, the RISC-V instruction set architecture, quick overview of superscalar architectures, VLIW architectures, instruction scheduling DESIGN OF SPECIAL PURPOSE CO-PROCESSORS case study: vector processors for high performance computing and embedded computing

knowledge of hardware description languages, digital circuits

Waine Wolf, Modern VLSI Design, Prentice Hall. Hennessy, J., Patterson, D., Computer Architecture: a quantitative approach, Elsevier. Hennessy, J., Patterson, D., Computer Organization and Design - RISC-V Edition, Elsevier Slides and articles available at: http://vlsi.diet.uniroma1.it and on the Google Classroom

lectures, flipped class exercises, occasionalmente lezioni in remoto

written and oral exam + compulsory student project

to be specified in the classroom

lectures, flipped class exercises, occasionalmente lezioni in remoto